In an application field, where a code division multiplex signal is required, such as the SSC, etc. it is required for a pseudo random noise code generator (hereinbelow called simply code generator) to be able to change its output code pattern. Heretofore a circuit structure as indicated in FIG. 6 has been utilized for the code generator capable of generating an arbitrary m sequence code according to an external control on the code period, the code pattern and the code phase.
In FIG. 6, SR.sub.1 to SR.sub.n-1 and SR.sub.f are flipflops and E.sub.2 to E.sub.n are exclusive logic sum gates, these two sorts of elements constituting a modular type shift register. Further MUX1 is a multiplexer controlling the number of stages of the modular type shift register stated above; AN.sub.2 to AN.sub.n are AND gates specifying the presence or absence of the feed back of a signal from the last output to each of the stages of the modular type shift register; and DS.sub.1 to DS.sub.n are data select circuits setting an initial value of the modular type shift register described above. That is, data c.sub.1 to c.sub.i perform the address assignment of the multiplexer MUX1 and determine the number of stages of the modular type shift register and thus the code period. On the other hand, data a.sub.2 to a.sub.n determine the feedback state of the signal from the last stage to each of the stages of the modular type shift register and thus the code pattern. Finally data b.sub.1 to b.sub.n determine the initial value of the modular type shift register and thus the code phase. In this way, the code period, the code pattern and the code phase can be controlled independently from each other so that an arbitrary m sequence code can be generated. These three sorts of data necessary for controlling the code are inputted in time sharing through common data lines DAT1 to DAT.sub.n for the purpose of reducing the number of input terminals. LAT1, LAT3 and LAT4 are latch circuits for inputting and holding the code pattern data a.sub.2 to a.sub.n, the code phase data b.sub.1 to b.sub.n and the code period data c.sub.1 to c.sub.i, respectively. DEC1 is a decoder circuit for selecting the latch circuits, in which the data should be written, using 2-bit signals SEL0 and SEL1. Since the output of the decoder circuit becomes active, only when a latch enable signal LE is at the "H" level, it is possible to control the timing of writing the data in the latch circuit by using the latch enable signal. After the setting of the code data, the output of a new code is started by an STB signal. At this time, in order that the code is not switched over during the setting of the code data, the code pattern data and the code period data are held in latch circuits having a double structure by means of LAT2 and LAT5. Further CLK represents a clock signal input terminal and CODE indicates a code output terminal.
Now, in the code division multiplex communication, for the reason of secrecy of signals, prevention of cross-talk and use of multiple channels, a GOLD code, which has a number of patterns much greater than that of the m sequence code having a same code period, is often used. The GOLD code is a code obtained by adding a plurality of m sequence codes having a same period but different patterns mod.2. It is known that (2.sup.n-1).multidot. (r-1) kinds of patterns can be obtained from r m sequence codes. FIG. 7 shows an example of the circuit structure, in the case where the GOLD code is obtained by using a prior art type of code generator. In FIG. 7, PNG1 and PNG2 are code generators having the structure indicated in FIG. 6; E1 is an exclusive logic sum gate for effecting the addition mod.2; and FF1 is a flipflop disposed for removing hazards produced in the exclusive logic sum gate E1 due to a difference in the delay time between the code generators PNG1 and PNG2 to obtain a code output in synchronism with the clock. In general, (2.sup.n-1 ) GOLD codes can be obtained, starting from 2 m sequence codes having a period of (2.sup.n-1) by varying the mutual phase difference therebetween. By means of the circuit indicated in FIG. 7 a still greater number of GOLD codes can be obtained by varying the pattern of the m sequence codes.
As explained above, the code generator having the structure indicated in FIG. 6 can be utilized in the code division multiplex communication such as the SSC, etc., owing to the fact that an arbitrary number of m sequence codes can be obtained by setting the code data from the exterior. However, it had a drawback that although it can be used for multiple purposes, the three sorts of data should be given from the exterior, every time the code is switched over. In particular, in an SSC using a convolver, etc., as indicated in FIG. 8, since a received signal P.sub.1 and a reference signal P.sub.2 are inputted through the two extremities of the convolver to obtain the correlation therebetween, the forwarding direction of the code P.sub.1 on the transmitter side is opposite to that of the code P.sub.2 on the receiver side, it is necessary to use a mirror image code at the transmission and reception. Consequently the prior art code generator had a drawback that different code data should be given for the transmission and the reception.
Further, in the field of the code division multiplex communication such as the SSC, etc., for the reason of secrecy of signals, prevention of cross-talk and use of multiple channels, it is advantageous to use the GOLD code, which has a number of code patterns much greater than that of the m sequence code having a same code period.
Now the structure of a code generator capable of dealing with the code shift keying (hereinbelow abbreviated to CSK) is considered. The CSK is a communication system, by which two kinds of codes are made correspond to information "0" and "1". Consequently, in order that the CSK can be effected, 2 kinds of GOLD codes should be generated simultaneously. As a method, by which a plurality of GOLD codes are generated simultaneously by 2 m sequence code generators, heretofore there was known e.g. that disclosed in Japanese patent application 63-200825, filed Aug. 10, 1988, by the same applicant. It is a method for obtaining GOLD codes having different patterns by using, apart from a code output from an m sequence code generator, a code having a delayed phase obtained by inputting the code output in a flipflop and by being based on a code output from another m sequence code generator together therewith. FIG. 9 shows an example of the structure of a code generator for the CSK using this method.
In FIG. 9, MSRG1 and MSRG2 are modular type shift register circuits, each of which consists of n stages; E1 and E2 are exclusive logic sum gates generating a GOLD code by adding 2 m sequence codes mod.2; FF1, FF2 and FF3 are flipflops for removing hazards produced in the exclusive logic sum gates to obtain a code output in synchronism with a clock signal: PTN1 and PTN2 are memory circuits for holding code pattern data specifying a feedback wiring method for the modular type shift register circuits MSRG1 and MSRG2; and LAT1 is a latch circuit, in which code phase data specifying the initial state of the shift register MSRG2 are inputted from the exterior and held. Further DS1 is a data select circuit, which selects one of the outputs of the gates E1 and E2 to output it to the flipflop FF3; and DS2 is a data select circuit, which gives a flipflop FF4 an initial value, when an output of the code is started by a STB signal. Still further, FF4 is a flipflop for obtaining a code output having a phase delayed by 1 chip with respect to the code output of the shift register MSRG2 through a terminal SI.sub.n.
For explaining the operation, the m sequence codes obtained through terminals CO of the shift registers MSRG1 and MSRG2 are represented by u and v, respectively, by the vector representation and a state transition matrix by T. Since the terminal SI.sub.n of each of the shift registers MSRG1 and MSRG2 takes out an input signal to the flipflop in the last stage in the relevant modular type shift register (i.e. flipflop, with the output of which the terminal CO is connected), the codes obtained through the terminals SI.sub.n are Tu and Tv, which have phases advanced by 1 chip with respect to u and v, respectively. Consequently the output of the gate E1 is Tu.sym.Tv; the output of the flipflop FF4 is v; and the output of the gate E2 is Tu.sym.v. In this way, it can be understood that GOLD codes having different patterns u.sym.v and u.sym.T.sup.-1 v are obtained at terminals GOLD1 and GOLD2, where the phase is delayed by one chip by one respective flipflop. Further, a code u.sym.v or u.sym.T.sup.-1 v is outputted through a terminal CSK for the CSK output, depending on the state of a signal CSK1, and thus it can be understood that the CSK is possible.
Now, by this system, since the phase of the code outputted by the shift register MSRG2 can be changed by the external control, the pair of the two codes used for the CSK can be expressed generally by u.sym.T.sup.i u and u.sym. T.sup.i31 1 u, where i is an arbitrary integer. Consequently, in order that the code of one channel does not overlap the code of another in the CSK, a condition expressed e.g. by the following equation should be fulfilled; EQU i=2m(0.ltoreq.m.ltoreq.2.sup.n31 1 -1) (1)
where m is an integer.
However, since an m sequence code generator consisting of n stages can be considered as a counting circuit, which counts numbers of 1 to 2.sup.n-1 (decimal) at random, it is obvious that it cannot be dealt with only by giving an even number as an initial state. In order to give code phase data satisfying the condition expressed by Equation (1), it is necessary to deduce a state equation from the structure of the code generator and to analyze the initial state.
As described above, it is possible to construct easily a code generator, which can deal with the CSK by applying the system stated above. However, for the application of the system stated above, it is necessary to analyze the set code data. Therefore, it had a drawback that the advantage that the code data of the code generator having the structure indicated in FIG. 10 can be assigned to the channel number; as they are, is lost.
Still further, although the code generator according to the prior art system can deal with the generation of various kinds of codes, when the use thereof in practice is taken into account, it has the following drawbacks;
(1) For every selection of the channel, i.e. for every setting of the code it is necessary to give a plurality of code generators three sorts of code data, i.e. code period, code pattern and code phase.
(2) It is necessary to obtain previously the code data necessary for setting a desired channel, i.e. a desired code by analysis, etc.
Consequently, in some respects, it was very difficult for users, who are not well acquainted with the structure of the code generator and how to use it, to make the best thereof.